The present invention relates to a semiconductor device wherein a plurality of types of semiconductor chips are held in a single package from an MCM (Multi Chip Module)-based approach so that signals can be inputted thereto and outputted therefrom with respect to each other, and particularly to a technique effective for application to a semiconductor device wherein a microcomputer including a CPU (Central Processing Unit), a programmable non-volatile memory such as a flash memory or the like, a DRAM (Dynamic Random Access Memory), and a logic LSI such as an ASIC (Application Specific Integrated Circuit) or the like are brought into one package.
The present inventors have discussed a technique wherein in a semiconductor device about a system on-chip, a plurality of types of semiconductor chips are accommodated or held in a single package so as to be able to input signals thereto and output the same therefrom with respect to each other from an MCM-based approach without bringing all of a microcomputer, a flash memory, a DRAM, an ASIC, etc. into one chip upon implementation of an approach to a DRMA/SIMM (Single In-line memory Module) having the high needs of users and a flash memory/DRAM-based microcomputer on-chip. The following is the corresponding technique discussed by the present inventors. Its summary is as follows:
A move attempt to form a microcomputer, a flash memory, a DRAM, an ASIC, etc. on one chip thereby to achieve the speeding up of a data transfer rate, space saving (improvements in packing density), low power consumption, etc. has recently been made active in front end technology such as a multimedia, information communications, etc. However, the formation of such many kinds of LSIs on one chip will cause an extreme increase in the load on a semiconductor manufacturing process.
This reason will be described below based on a process for placing or forming the microcomputer, flash memory, DRAM and ASIC in mixed form, which has been discussed by the present inventors. A summary of the mixed-loading process is as follows:
A p-type impurity (boron) is ion-implanted in a principal surface of a semiconductor substrate 100 to form a p well 101 as shown in FIG. 78. Thereafter, a field oxide film 102 is formed over the surface of the p well 101 by a LOCOS method. An element or device formed at the left end in the drawing is a MOSFET which constitutes each memory cell of a DRAM, devices formed at a position adjacent to the right side are a MOSFET which constitutes each memory cell of a flash memory and a MOSFET for a high voltage, which constitutes part of a peripheral circuit of the flash memory. A device formed at the right end is a MOSFET which constitutes a logic LSI such as a microcomputer, an ASIC or the like. Incidentally, an actual LSI is comprised principally of an n channel MOSFET and a p channel MOSFET. However, only a region for forming the n channel MOSFET will be illustrated to simplify its description.
Next, a tunnel oxide film 103 for the flash memory is formed as shown in FIG. 79. The thickness of the tunnel oxide film 103 is set so as to range from about 8 nm to 13 nm.
Next, as shown in FIG. 80, a polycrystal silicon film deposited on the semiconductor substrate 100 by CVD is subjected to patterning to form a floating gate 104 (part thereof) for the flash memory. Thereafter, a silicon oxide film, a silicon nitride film and a silicon oxide film are layered over the floating gate 104 as shown in FIG. 81 thereby to form a second insulating film (ONO film) 105 whose thickness ranges from about 10 nm to 30 nm.
Next, a gate oxide film 106 for the MOSFET which withstands a high voltage, is formed in a peripheral circuit region of the flash memory as shown in FIG. 82. The gate oxide film 106 is formed to a thickness (which ranges from 10 nm to 30 nm) thicker than the thicknesses of gate oxide films for other MOSFETs.
Next, a gate oxide film 107 for the MOSFET which constitutes the logic LSI, and a gate oxide film 130 for the MOSFET which constitutes each memory cell for DRAM, are formed as shown in FIG. 83. The thickness of the gate oxide film 107 is set so as to range from about 4 nm to 10 nm, whereas the thickness of the gate oxide film 130 is set so as to range from about 8 nm to 15 nm.
Next, as shown in FIG. 84, the polycrystal silicon film deposited over the semiconductor substrate 100 by CVD is subjected to patterning thereby to simultaneously form gate electrodes (word lines) for each individual memory cells of the DRAM, a control gate 109 for the flash memory, a gate electrode 110 for the high-withstand MOSFET, a gate electrode 111 for the MOSFET which constitutes the logic LSI. Thereafter, the (partly-formed) floating gate 104 for the flash memory is subjected to patterning to form a floating gate 104 as shown in FIG. 85.
Next, n-type impurities (phosphorus and arsenic) are ion-implanted in part of a memory cell region of the flash memory as shown in FIG. 86 to form an n+-type semiconductor region 112 for the flash memory. Thereafter, the n-type impurities (phosphorus and arsenic) are ion-implanted in part of the memory cell region of the flash memory, the peripheral circuit region thereof and a logic LSI forming region as shown in FIG. 87 thereby to simultaneously form nxe2x88x92-type semiconductor regions 113 and 113 for the flash memory, nxe2x88x92-type semiconductor regions 113 and 113 for the high-withstand MOSFET, and nxe2x88x92-type semiconductor regions 113 and 113 for the MOSFET which constitutes the logic LSI.
Next, as shown in FIG. 88, side wall spacers 114 are respectively formed over the side walls of the gate electrodes (word lines) 108 for each individual memory cells of DRAM, the control gate 109 for the flash memory, the gate electrode 110 for the MOSFET for a high voltage, and the gate electrode 111 for the MOSFET which constitutes the logic LSI.
Next, the n-type impurities (phosphorus and arsenic) are ion-implanted in part of the memory cell region of the flash memory, the peripheral circuit region and the logic LSI forming region as shown in FIG. 89 to simultaneously form an n+-type semiconductor region 115 for the flash memory, n+-type semiconductor regions 115 and 115 for the high-withstand MOSFET, and n+-type semiconductor regions 115 and 115 for the MOSFET which constitutes the logic LSI, whereby one of a source region and a drain region for the flash memory, a source region and a drain region for the high-withstand MOSFET, and a source region and a drain region for the MOSFET constituting the logic LSI are brought to an LDD (Lightly Doped Drain) structure.
Next, as shown in FIG. 90, a silicon oxide film 116 deposited over the semiconductor substrate 100 by CVD is etched to define connecting holes on both sides of the gate electrodes (word lines) of the DRAM and define a connecting hole in an upper portion of the n+-type semiconductor region 112 for the flash memory. Thereafter, plugs 117 each composed of a polycrystal silicon film are formed inside these connecting holes. On both sides of the gate electrodes of the DRAM, n-type semiconductor regions 118 are formed by impurities diffused from the polycrystal silicon film. Thereafter, the polycrystal silicon film deposited over the silicon oxide film 116 by CVD is subjected to patterning to form each bit line BL for the DRAM and each bit line BL for the flash memory.
Next, a silicon oxide film 119 is deposited over the semiconductor substrate 100 by CVD as shown in FIG. 91. Thereafter, a polycrystal silicon film deposited over the silicon oxide film 119 is subjected to patterning to form lower electrodes 120 of capacitors for the DRAM.
A tantalum oxide film (or nitride silicon film) and the polycrystal silicon film deposited over the semiconductor substrate 100 are patterned to form an capacitive insulating film 121 and an upper electrode 122 of each capacitor for the DRAM as shown in FIG. 92. Thereafter, a silicon oxide film 123 is deposited over the semiconductor substrate 100 by CVD as shown in FIG. 93. An A1 film deposited over the silicon oxide film 123 is subjected to patterning to form metal wires or interconnections 124 as a first layer. Afterwards, a silicon oxide film 125 is deposited over the semiconductor substrate 100 by CVD as shown in FIG. 94. Thereafter, an A1 film deposited over the silicon oxide film 125 is subjected to patterning to form metal interconnections 126 as a second layer.
The above description is the summary of the process for forming the microcomputer, flash memory, DRAM and ASIC in mixed form.
According to the discussions of the present inventors, the above-described process has the following problems.
(1) The attainment of the speeding up of a logic unit needs to shorten a gate length of each MOSFET and thin the thickness of a gate oxide film. On the other hand, it is necessary to make the thickness of a gate oxide film of each MOSFET for a DRAM thicker than that of a gate oxide film of each MOSFET for the logic unit to some extent in consideration of a withstand voltage or high voltage. Further, a gate oxide film of each high-withstand MOSFET for a flash memory to which a high voltage is applied, needs to have a thicker thickness in order to ensure a sufficient withstand voltage. That is, when the DRAM, logic and flash memory are placed in mixed form, it is necessary to provide gate oxide films having thicknesses which vary according to required power levels. Therefore, the number of process steps and the number of masks increase by a large amount.
(2) When a DRAM is comprised of one transistor+one capacitor, a high-temperature heat treatment (corresponding to heat treatment for stabilizing the tantalum oxide film or high-temperature nitriding treatment) is taken upon formation of the capacitor. It is therefore necessary to set the gate length at the logic unit longer more or less. However, when the gate length at the logic unit is made longer, the speeding up of the logic unit will fall a sacrifice.
(3) Since the height of the DRAM on the semiconductor chip is higher than the logic unit and there is a step-like offset between the two, this exerts a bad influence on wiring formation. This tendency becomes pronounced in the case of a DRAM which adopts a stacked capacitor (Stacked Capacitor) structure in particular.
Thus, when one attempts to achieve one chip while the respective performance of the DRAM, logic, and flash memory are being maintained together, the number of process steps and the number of masks greatly increase. Alternatively, a mixed-loading process suitable for the achievement of one chip must be developed again. Even in either case, the manufacturing cost greatly increases.
There is also a strong demand for the loading of both a flash memory and a DRAM into a microcomputer system including a CPU even from a circuital standpoint based on a functional block configuration in addition to the above-described manufacturing process-based cost analysis. When the packageability to a built-in apparatus is taken into consideration, the integration of the two types of semiconductor chips comprised of the flash memory and DRAM into one package is indispensable. Therefore, the present inventors have thought that a decrease in the number of external connecting terminals and a reduction in the packing area due to the integration of a plurality of types of semiconductor chips into one package could be achieved by assigning signals used in common to the mutual semiconductor chips to common external connecting terminals respectively, and the costdown to the microcomputer system could be achieved even from the circuital standpoint.
An object of the present invention is to provide a semiconductor device wherein in a package structure of a type wherein two types of semiconductor chips corresponding to a CPU and a flash memory, and a DRAM are integrated or combined into one package, a decrease in the number of external connecting terminals and a reduction in the packing area due to the integration of the two types of semiconductor chips into one package can be achieved even from a circuital standpoint based on a functional block configuration, and the costdown to a microcomputer system can be achieved.
Another object of the present invention is to provide a semiconductor device wherein when a DRAM is set as a synchronous DRAM where a logic circuit such as an ASIC or the like is incorporated into respective semiconductor chips, external connecting terminals can be further made common, thereby making it possible to provide a much further reduction in the number of external connecting terminals and achieve the costdown thereto.
A further object of the present invention is to provide the above-described semiconductor device at low cost.
When two types of semiconductor chips corresponding to a so-called flash memory-equipped microcomputer, which is equipped with a CPU and a flash memory, for example, and a semiconductor chip referred to as so-called DRAM on-chip logic, which is equipped with a DRAM and a logic circuit such as an ASIC or the like are considered in the above-described microcomputer system, it is essential that countermeasures against the operation between the flash memory-equipped microcomputer and the DRAM on-chip logic should be taken. In other words, it is necessary to take countermeasures against data transfer rates with respect to an access operation to the DRAM of the DRAM on-chip logic from the flash memory-equipped microcomputer and an access operation to the DRAM from the logic circuit inside the DRAM on-chip logic.
When it is desired to connect between the semiconductor chips respectively corresponding to the aforementioned flash memory-equipped microcomputer and DRAM on-chip logic at high speed, for example, they can be connected to each other at high speed by using an interface directly coupled to the DRAM. However, if the logic circuit of the DRAM on-chip logic desires to access the DRAM, then there is known, as a first method, a method of sending a wait signal back to the CPU when the logic circuit is in operation. Since the present method must use an asynchronous memory as a memory to be handled between the flash memory-equipped microcomputer and the DRAM on-chip logic, the transfer of data in one clock cycle cannot be performed, i.e., the transfer of data in two-clock cycle is performed because the time required to read or recognize the wait signal cannot be taken or spent.
As a second method capable of implementing one clock cycle, may be mentioned a method of allowing the flash memory-equipped microcomputer to perform bus arbitration in the on-chip logic itself. According to this method, since the logic circuit of the DRAM on-chip logic outputs a request signal for making a request to the CPU for a bus release and the CPU cannot do anything during a period in which a bus is set free to the logic circuit, the present method will cause a malfunction or inconvenience that overheads of the arbitration increase and the CPU itself cannot perform time-based control.
Therefore, the present inventors have focused attention on the fact that the time may preferably be controlled by the CPU itself of the flash memory-equipped microcomputer. The present inventors thought from such attention that a self-refresh period of the DRAM as viewed from the flash memory-equipped microcomputer was effectively used to thereby allow a self-refresh operation of the DRAM, and an access operation to the DRAM from the logic circuit lying inside the DRMA on-chip logic was made possible during this self-refresh period, whereby the transfer of data between the flash memory-equipped microcomputer and the DRAM on-chip logic could be achieved at high speed.
One object of the present invention is to provide a semiconductor device wherein in semiconductor chips each equipped with a DRAM and a logic circuit such as an ASIC or the like, the need for wait control is eliminated and a self-refresh period of the DRAM as viewed from the outside is effectively used to thereby allow an access operation to the DRAM from the logic circuit during this self-refresh period, whereby the speeding up of the transfer of data between the outside and each semiconductor chip can be implemented.
The present invention also provides a semiconductor device wherein even in the case of a package structure in which two types of chips corresponding to a semiconductor chip equipped with a DRAM and a logic circuit and a semiconductor chip equipped with a CPU and a flash memory are combined into one package, wait control is made unnecessary and an access operation to the DRAM from the logic circuit is made possible during a self-refresh period of the DRAM as viewed from the CPU, whereby the speeding up of the transfer of data between the semiconductor chips can be implemented.
Further, the present invention provides a semiconductor device capable of facilitating the creation of programs since wait control used to perform wait-signal exchanges becomes unnecessary and timing itself provided for processing can be controlled from a CPU.
Moreover, the present invention provides a semiconductor device wherein the use of a general-purpose DRAM interface makes it possible to directly connect a semiconductor chip equipped with a DRAM and a logic circuit and a semiconductor chip equipped with a CPU and a flash memory to one another so that they are operable at high speed.
The above and other objects of the present invention and novel features thereof will become apparent from the following description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
That is, the present invention provides one semiconductor device comprising a stacked package in which a plurality of tape carriers which seal a plurality of semiconductor chips, are stacked on one another in upward and downward directions, and wherein connecting terminals shared between the plurality of semiconductor chips are drawn to the same external connecting terminals of the stacked package through conductive layers formed in the tape carriers.
The present invention provides another semiconductor device wherein one ends of leads formed over the whole surface of each tape carrier referred to above are respectively electrically connected to connecting terminals of each semiconductor chip referred to above, the other ends of the leads are respectively electrically connected to through holes defined in each tape carrier, and the connecting terminals common to the plurality of semiconductor chips are formed at the same positions of the plurality of tape carriers and withdrawn to the same external connecting terminals via a plurality of mutually-penetrated through holes.
The present invention provides a further semiconductor device wherein the external connecting terminals are solder bumps formed at one ends of the through holes of the tape carrier corresponding to the lowest layer.
The present invention provides a still further semiconductor device wherein the external connecting terminals are formed over the whole surface of the tape carrier corresponding to the lowest layer and one ends thereof are leads which protrude to the outside of the tape carrier.
The present invention provides a still further semiconductor device wherein the external connecting terminals include some used as conductive pins, which are inserted into the through holes and others used as conductive pins, which protrude to the outside of the tape carrier.
The present invention provides a still further semiconductor device wherein one ends of the leads formed over the whole surface of each tape carrier referred to above are electrically connected to the connecting terminals of each semiconductor chip referred to above and the other ends of the leads protrude to the outside of each tape carrier so as to form the external connecting terminals, and a plurality of leads withdrawn from the connecting terminals common to the plurality of semiconductor chips are superimposed on one another in the outside of each tape carrier to thereby form common external connecting terminals.
The present invention provides a still further semiconductor device wherein one ends of the leads formed over the whole surface of each tape carrier referred to above are electrically connected to the connecting terminals of each semiconductor chip referred to above and the other ends of the leads protrude to the outside of each tape carrier so as to form the external connecting terminals, and a plurality of leads withdrawn from the connecting terminals common to the plurality of semiconductor chips are joined onto common electrodes of a mounting substrate.
The above and other objects of the present invention and novel features thereof will become apparent from the following description of the present specification and the accompanying drawings.